[AMDGPU][MC] Replace shifted registers in CFI instructions #164726

slinder1 · 2025-10-22T22:28:12Z

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slinder1 · 2025-10-22T22:28:28Z

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[AMDGPU][MC] Replace shifted registers in CFI instructions #164726 👈 (View in Graphite)
[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs #164725
[AMDGPU] Implement CFI for CSR spills #164724
[AMDGPU] Implement CFI for non-kernel functions #164723
[AMDGPU] Emit entry function Dwarf CFI #164722
[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU #164721 : 1 other dependent PR (#166464 )
[MC] Use a variant to hold MCCFIInstruction state (NFC) #164720
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llvmbot · 2025-10-22T22:39:49Z

@llvm/pr-subscribers-debuginfo

@llvm/pr-subscribers-llvm-mc

Author: Scott Linder (slinder1)

Changes

Patch is 28.92 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/164726.diff

10 Files Affected:

(modified) llvm/include/llvm/CodeGen/MachineFunction.h (+4)
(modified) llvm/include/llvm/MC/MCDwarf.h (+3)
(modified) llvm/lib/CodeGen/MachineFunction.cpp (+10)
(modified) llvm/lib/MC/MCDwarf.cpp (+33)
(modified) llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (+3)
(modified) llvm/test/CodeGen/AMDGPU/debug-frame.ll (+4-4)
(modified) llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll (+15-15)
(modified) llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir (+67-67)

diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index ef783f276b7d4..5db370c160ce3 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -1234,6 +1234,10 @@ class LLVM_ABI MachineFunction {
 
   [[nodiscard]] unsigned addFrameInst(const MCCFIInstruction &Inst);
 
+  /// Replace all references to register \param From with register \param To in
+  /// frame instructions. Note that .cfi_escape instructions will be left as-is.
+  void replaceFrameInstRegister(Register From, Register To);
+
   /// Returns a reference to a list of symbols immediately following calls to
   /// _setjmp in the function. Used to construct the longjmp target table used
   /// by Windows Control Flow Guard.
diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h
index e602f03de5ebf..9df687c282a0c 100644
--- a/llvm/include/llvm/MC/MCDwarf.h
+++ b/llvm/include/llvm/MC/MCDwarf.h
@@ -837,6 +837,9 @@ class MCCFIInstruction {
     return std::get<EscapeFields>(ExtraFields).Comment;
   }
   SMLoc getLoc() const { return Loc; }
+
+  /// Replaces in place all references to FromReg with ToReg.
+  void replaceRegister(unsigned FromReg, unsigned ToReg);
 };
 
 struct MCDwarfFrameInfo {
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index bfa5ab274c686..69836ef27f8c3 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -336,6 +336,16 @@ MachineFunction::addFrameInst(const MCCFIInstruction &Inst) {
   return FrameInstructions.size() - 1;
 }
 
+void MachineFunction::replaceFrameInstRegister(Register FromReg,
+                                               Register ToReg) {
+  const MCRegisterInfo *MCRI = Ctx.getRegisterInfo();
+  unsigned DwarfFromReg = MCRI->getDwarfRegNum(FromReg, false);
+  unsigned DwarfToReg = MCRI->getDwarfRegNum(ToReg, false);
+
+  for (MCCFIInstruction &Inst : FrameInstructions)
+    Inst.replaceRegister(DwarfFromReg, DwarfToReg);
+}
+
 /// This discards all of the MachineBasicBlock numbers and recomputes them.
 /// This guarantees that the MBB numbers are sequential, dense, and match the
 /// ordering of the blocks within the function.  If a specific MachineBasicBlock
diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp
index 09a93dd34ece3..b9d8783009376 100644
--- a/llvm/lib/MC/MCDwarf.cpp
+++ b/llvm/lib/MC/MCDwarf.cpp
@@ -1292,6 +1292,39 @@ void MCGenDwarfLabelEntry::Make(MCSymbol *Symbol, MCStreamer *MCOS,
       MCGenDwarfLabelEntry(Name, FileNumber, LineNumber, Label));
 }
 
+void MCCFIInstruction::replaceRegister(unsigned FromReg, unsigned ToReg) {
+  auto ReplaceReg = [=](unsigned &Reg) {
+    if (Reg == FromReg)
+      Reg = ToReg;
+  };
+  auto Visitor = makeVisitor(
+      [=](CommonFields &F) {
+        ReplaceReg(F.Register);
+        ReplaceReg(F.Register2);
+      },
+      [](EscapeFields &) {}, [](LabelFields &) {},
+      [=](RegisterPairFields &F) {
+        ReplaceReg(F.Register);
+        ReplaceReg(F.Reg1);
+        ReplaceReg(F.Reg2);
+      },
+      [=](VectorRegistersFields &F) {
+        ReplaceReg(F.Register);
+        for (auto &VRL : F.VectorRegisters)
+          ReplaceReg(VRL.Register);
+      },
+      [=](VectorOffsetFields &F) {
+        ReplaceReg(F.Register);
+        ReplaceReg(F.MaskRegister);
+      },
+      [=](VectorRegisterMaskFields &F) {
+        ReplaceReg(F.Register);
+        ReplaceReg(F.SpillRegister);
+        ReplaceReg(F.MaskRegister);
+      });
+  std::visit(Visitor, ExtraFields);
+}
+
 static int getDataAlignmentFactor(MCStreamer &streamer) {
   MCContext &context = streamer.getContext();
   const MCAsmInfo *asmInfo = context.getAsmInfo();
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index 2c275a85440d9..c6dc40c0b3ef0 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -386,6 +386,9 @@ void SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange(
     if (RegItr != SpillPhysVGPRs.end()) {
       unsigned Idx = std::distance(SpillPhysVGPRs.begin(), RegItr);
       SpillPhysVGPRs[Idx] = NewReg;
+
+      // For replacing registers used in the CFI instructions.
+      MF.replaceFrameInstRegister(Reg, NewReg);
     }
 
     // The generic `determineCalleeSaves` might have set the old register if it
diff --git a/llvm/test/CodeGen/AMDGPU/debug-frame.ll b/llvm/test/CodeGen/AMDGPU/debug-frame.ll
index c3c93c1b606ec..5fa5452aba86e 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-frame.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-frame.ll
@@ -2449,7 +2449,7 @@ define hidden void @func_call_clobber() #0 {
 ; GFX900-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX900-NEXT:    s_addk_i32 s32, 0x400
 ; GFX900-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX900-NEXT:    .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
+; GFX900-NEXT:    .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
 ; GFX900-NEXT:    s_getpc_b64 s[16:17]
 ; GFX900-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
 ; GFX900-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
@@ -2723,7 +2723,7 @@ define hidden void @func_call_clobber() #0 {
 ; GFX90A-V2A-DIS-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX90A-V2A-DIS-NEXT:    s_addk_i32 s32, 0x400
 ; GFX90A-V2A-DIS-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX90A-V2A-DIS-NEXT:    .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
+; GFX90A-V2A-DIS-NEXT:    .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
 ; GFX90A-V2A-DIS-NEXT:    s_getpc_b64 s[16:17]
 ; GFX90A-V2A-DIS-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
 ; GFX90A-V2A-DIS-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
@@ -2997,7 +2997,7 @@ define hidden void @func_call_clobber() #0 {
 ; GFX90A-V2A-EN-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX90A-V2A-EN-NEXT:    s_addk_i32 s32, 0x400
 ; GFX90A-V2A-EN-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX90A-V2A-EN-NEXT:    .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
+; GFX90A-V2A-EN-NEXT:    .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
 ; GFX90A-V2A-EN-NEXT:    s_getpc_b64 s[16:17]
 ; GFX90A-V2A-EN-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
 ; GFX90A-V2A-EN-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
@@ -3240,7 +3240,7 @@ define hidden void @func_call_clobber() #0 {
 ; WAVE32-NEXT:    v_writelane_b32 v40, s30, 0
 ; WAVE32-NEXT:    s_addk_i32 s32, 0x200
 ; WAVE32-NEXT:    v_writelane_b32 v40, s31, 1
-; WAVE32-NEXT:    .cfi_llvm_vector_registers 16, 1791, 0, 32, 1791, 1, 32
+; WAVE32-NEXT:    .cfi_llvm_vector_registers 16, 1576, 0, 32, 1576, 1, 32
 ; WAVE32-NEXT:    s_getpc_b64 s[16:17]
 ; WAVE32-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
 ; WAVE32-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
diff --git a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
index bc928041ed750..51300c363e611 100644
--- a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
@@ -493,36 +493,36 @@ define weak_odr void @test(i32 %0) !dbg !34 {
 ; CHECK-NEXT:    buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
 ; CHECK-NEXT:    .cfi_llvm_vector_offset 2600, 32, 17, 64, 0
 ; CHECK-NEXT:    v_writelane_b32 v41, s34, 0
-; CHECK-NEXT:    .cfi_llvm_vector_registers 66, 2622, 0, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 66, 2601, 0, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s35, 1
-; CHECK-NEXT:    .cfi_llvm_vector_registers 67, 2622, 1, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 67, 2601, 1, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s36, 2
-; CHECK-NEXT:    .cfi_llvm_vector_registers 68, 2622, 2, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 68, 2601, 2, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s37, 3
-; CHECK-NEXT:    .cfi_llvm_vector_registers 69, 2622, 3, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 69, 2601, 3, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s38, 4
-; CHECK-NEXT:    .cfi_llvm_vector_registers 70, 2622, 4, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 70, 2601, 4, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s39, 5
-; CHECK-NEXT:    .cfi_llvm_vector_registers 71, 2622, 5, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 71, 2601, 5, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s48, 6
-; CHECK-NEXT:    .cfi_llvm_vector_registers 80, 2622, 6, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 80, 2601, 6, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s49, 7
-; CHECK-NEXT:    .cfi_llvm_vector_registers 81, 2622, 7, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 81, 2601, 7, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s50, 8
-; CHECK-NEXT:    .cfi_llvm_vector_registers 82, 2622, 8, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 82, 2601, 8, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s51, 9
-; CHECK-NEXT:    .cfi_llvm_vector_registers 83, 2622, 9, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 83, 2601, 9, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s52, 10
-; CHECK-NEXT:    .cfi_llvm_vector_registers 84, 2622, 10, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 84, 2601, 10, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s53, 11
-; CHECK-NEXT:    .cfi_llvm_vector_registers 85, 2622, 11, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 85, 2601, 11, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s54, 12
-; CHECK-NEXT:    .cfi_llvm_vector_registers 86, 2622, 12, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 86, 2601, 12, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s55, 13
-; CHECK-NEXT:    .cfi_llvm_vector_registers 87, 2622, 13, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 87, 2601, 13, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s30, 14
 ; CHECK-NEXT:    v_writelane_b32 v41, s31, 15
-; CHECK-NEXT:    .cfi_llvm_vector_registers 16, 2622, 14, 32, 2622, 15, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 16, 2601, 14, 32, 2601, 15, 32
 ; CHECK-NEXT:    s_mov_b64 s[48:49], s[4:5]
 ; CHECK-NEXT:    ;DEBUG_VALUE: dummy:dummy <- undef
 ; CHECK-NEXT:  .Ltmp0:
diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
index e6d93d857d5a0..c7f751dd30e33 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
@@ -230,7 +230,7 @@ define fastcc i32 @foo() {
   ; CHECK-NEXT:   $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
   ; CHECK-NEXT:   $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc
   ; CHECK-NEXT:   $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31
-  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr127, 0, 32, $vgpr127, 1, 32
+  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr40, 0, 32, $vgpr40, 1, 32
   ; CHECK-NEXT:   BUNDLE implicit-def $sgpr16_sgpr17, implicit-def $sgpr16, implicit-def $scc, implicit-def $sgpr17 {
   ; CHECK-NEXT:     $sgpr16_sgpr17 = S_GETPC_B64
   ; CHECK-NEXT:     $sgpr16 = S_ADD_U32 internal $sgpr16, target-flags(amdgpu-gotprel32-lo) @bar + 4, implicit-def $scc
diff --git a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
index da30190663457..a87f8289e9d4b 100644
--- a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
@@ -233,7 +233,7 @@ define hidden void @_ZL3barv() #0 !dbg !1644 {
 ; CHECK-NEXT:    s_add_i32 s32, s32, 0x400
 ; CHECK-NEXT:    v_writelane_b32 v40, s30, 0
 ; CHECK-NEXT:    v_writelane_b32 v40, s31, 1
-; CHECK-NEXT:    .cfi_llvm_vector_registers 16, 2623, 0, 32, 2623, 1, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
 ; CHECK-NEXT:  .Ltmp0:
 ; CHECK-NEXT:    .loc 0 31 3 prologue_end ; lane-info.cpp:31:3
 ; CHECK-NEXT:    s_getpc_b64 s[16:17]
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
index b71a9eeef208e..2107c7bd527fc 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
@@ -91,140 +91,140 @@ body:             |
   ; GCN-NEXT:   frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02
   ; GCN-NEXT:   $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24, implicit-def dead $scc
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr4, $vgpr255, 0, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr4, $vgpr2, 0, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr5, $vgpr255, 1, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr5, $vgpr2, 1, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr6, 2, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr6, $vgpr255, 2, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr6, $vgpr2, 2, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr7, 3, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr7, $vgpr255, 3, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr7, $vgpr2, 3, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr8, 4, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr8, $vgpr255, 4, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr8, $vgpr2, 4, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr9, 5, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr9, $vgpr255, 5, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr9, $vgpr2, 5, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr10, 6, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr10, $vgpr255, 6, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr10, $vgpr2, 6, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr11, 7, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr11, $vgpr255, 7, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr11, $vgpr2, 7, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr12, 8, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr12, $vgpr255, 8, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr12, $vgpr2, 8, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr13, 9, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr13, $vgpr255, 9, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr13, $vgpr2, 9, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr14, 10, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr14, $vgpr255, 10, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr14, $vgpr2, 10, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr15, 11, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr15, $vgpr255, 11, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr15, $vgpr2, 11, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr16, 12, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr16, $vgpr255, 12, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr16, $vgpr2, 12, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr17, 13, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr17, $vgpr255, 13, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr17, $vgpr2, 13, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr18, 14, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr18, $vgpr255, 14, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr18, $vgpr2, 14, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr19, 15, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr19, $vgpr255, 15, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr19, $vgpr2, 15, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr20, 16, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr20, $vgpr255, 16, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr20, $vgpr2, 16, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr21, 17, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr21, $vgpr255, 17, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr21, $vgpr2, 17, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr22, 18, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr22, $vgpr255, 18, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr22, $vgpr2, 18, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr23, 19, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr23, $vgpr255, 19, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr23, $vgpr2, 19, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr24, 20, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr24, $vgpr255, 20, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr24, $vgpr2, 20, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr25, 21, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr25, $vgpr255, 21, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr25, $vgpr2, 21, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr26, 22, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr26, $vgpr255, 22, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr26, $vgpr2, 22, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr27, 23, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr27, $vgpr255, 23, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr27, $vgpr2, 23, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr28, 24, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr28, $vgpr255, 24, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr28, $vgpr2, 24, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr29, 25, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr29, $vgpr255, 25, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr29, $vgpr2, 25, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr64, 26, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr255, 26, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr2, 26, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr65, 27, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr255, 27, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr2, 27, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr66, 28, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr255, 28, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr2, 28, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr67, 29, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr255, 29, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr2, 29, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr68, 30, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr255, 30, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr2, 30, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr69, 31, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr69, $vgpr255, 31, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llv...
[truncated]

llvmbot · 2025-10-22T22:39:49Z

@llvm/pr-subscribers-backend-amdgpu

Author: Scott Linder (slinder1)

Changes

Patch is 28.92 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/164726.diff

10 Files Affected:

(modified) llvm/include/llvm/CodeGen/MachineFunction.h (+4)
(modified) llvm/include/llvm/MC/MCDwarf.h (+3)
(modified) llvm/lib/CodeGen/MachineFunction.cpp (+10)
(modified) llvm/lib/MC/MCDwarf.cpp (+33)
(modified) llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (+3)
(modified) llvm/test/CodeGen/AMDGPU/debug-frame.ll (+4-4)
(modified) llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll (+15-15)
(modified) llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir (+67-67)

diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index ef783f276b7d4..5db370c160ce3 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -1234,6 +1234,10 @@ class LLVM_ABI MachineFunction {
 
   [[nodiscard]] unsigned addFrameInst(const MCCFIInstruction &Inst);
 
+  /// Replace all references to register \param From with register \param To in
+  /// frame instructions. Note that .cfi_escape instructions will be left as-is.
+  void replaceFrameInstRegister(Register From, Register To);
+
   /// Returns a reference to a list of symbols immediately following calls to
   /// _setjmp in the function. Used to construct the longjmp target table used
   /// by Windows Control Flow Guard.
diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h
index e602f03de5ebf..9df687c282a0c 100644
--- a/llvm/include/llvm/MC/MCDwarf.h
+++ b/llvm/include/llvm/MC/MCDwarf.h
@@ -837,6 +837,9 @@ class MCCFIInstruction {
     return std::get<EscapeFields>(ExtraFields).Comment;
   }
   SMLoc getLoc() const { return Loc; }
+
+  /// Replaces in place all references to FromReg with ToReg.
+  void replaceRegister(unsigned FromReg, unsigned ToReg);
 };
 
 struct MCDwarfFrameInfo {
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index bfa5ab274c686..69836ef27f8c3 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -336,6 +336,16 @@ MachineFunction::addFrameInst(const MCCFIInstruction &Inst) {
   return FrameInstructions.size() - 1;
 }
 
+void MachineFunction::replaceFrameInstRegister(Register FromReg,
+                                               Register ToReg) {
+  const MCRegisterInfo *MCRI = Ctx.getRegisterInfo();
+  unsigned DwarfFromReg = MCRI->getDwarfRegNum(FromReg, false);
+  unsigned DwarfToReg = MCRI->getDwarfRegNum(ToReg, false);
+
+  for (MCCFIInstruction &Inst : FrameInstructions)
+    Inst.replaceRegister(DwarfFromReg, DwarfToReg);
+}
+
 /// This discards all of the MachineBasicBlock numbers and recomputes them.
 /// This guarantees that the MBB numbers are sequential, dense, and match the
 /// ordering of the blocks within the function.  If a specific MachineBasicBlock
diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp
index 09a93dd34ece3..b9d8783009376 100644
--- a/llvm/lib/MC/MCDwarf.cpp
+++ b/llvm/lib/MC/MCDwarf.cpp
@@ -1292,6 +1292,39 @@ void MCGenDwarfLabelEntry::Make(MCSymbol *Symbol, MCStreamer *MCOS,
       MCGenDwarfLabelEntry(Name, FileNumber, LineNumber, Label));
 }
 
+void MCCFIInstruction::replaceRegister(unsigned FromReg, unsigned ToReg) {
+  auto ReplaceReg = [=](unsigned &Reg) {
+    if (Reg == FromReg)
+      Reg = ToReg;
+  };
+  auto Visitor = makeVisitor(
+      [=](CommonFields &F) {
+        ReplaceReg(F.Register);
+        ReplaceReg(F.Register2);
+      },
+      [](EscapeFields &) {}, [](LabelFields &) {},
+      [=](RegisterPairFields &F) {
+        ReplaceReg(F.Register);
+        ReplaceReg(F.Reg1);
+        ReplaceReg(F.Reg2);
+      },
+      [=](VectorRegistersFields &F) {
+        ReplaceReg(F.Register);
+        for (auto &VRL : F.VectorRegisters)
+          ReplaceReg(VRL.Register);
+      },
+      [=](VectorOffsetFields &F) {
+        ReplaceReg(F.Register);
+        ReplaceReg(F.MaskRegister);
+      },
+      [=](VectorRegisterMaskFields &F) {
+        ReplaceReg(F.Register);
+        ReplaceReg(F.SpillRegister);
+        ReplaceReg(F.MaskRegister);
+      });
+  std::visit(Visitor, ExtraFields);
+}
+
 static int getDataAlignmentFactor(MCStreamer &streamer) {
   MCContext &context = streamer.getContext();
   const MCAsmInfo *asmInfo = context.getAsmInfo();
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index 2c275a85440d9..c6dc40c0b3ef0 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -386,6 +386,9 @@ void SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange(
     if (RegItr != SpillPhysVGPRs.end()) {
       unsigned Idx = std::distance(SpillPhysVGPRs.begin(), RegItr);
       SpillPhysVGPRs[Idx] = NewReg;
+
+      // For replacing registers used in the CFI instructions.
+      MF.replaceFrameInstRegister(Reg, NewReg);
     }
 
     // The generic `determineCalleeSaves` might have set the old register if it
diff --git a/llvm/test/CodeGen/AMDGPU/debug-frame.ll b/llvm/test/CodeGen/AMDGPU/debug-frame.ll
index c3c93c1b606ec..5fa5452aba86e 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-frame.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-frame.ll
@@ -2449,7 +2449,7 @@ define hidden void @func_call_clobber() #0 {
 ; GFX900-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX900-NEXT:    s_addk_i32 s32, 0x400
 ; GFX900-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX900-NEXT:    .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
+; GFX900-NEXT:    .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
 ; GFX900-NEXT:    s_getpc_b64 s[16:17]
 ; GFX900-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
 ; GFX900-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
@@ -2723,7 +2723,7 @@ define hidden void @func_call_clobber() #0 {
 ; GFX90A-V2A-DIS-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX90A-V2A-DIS-NEXT:    s_addk_i32 s32, 0x400
 ; GFX90A-V2A-DIS-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX90A-V2A-DIS-NEXT:    .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
+; GFX90A-V2A-DIS-NEXT:    .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
 ; GFX90A-V2A-DIS-NEXT:    s_getpc_b64 s[16:17]
 ; GFX90A-V2A-DIS-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
 ; GFX90A-V2A-DIS-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
@@ -2997,7 +2997,7 @@ define hidden void @func_call_clobber() #0 {
 ; GFX90A-V2A-EN-NEXT:    v_writelane_b32 v40, s30, 0
 ; GFX90A-V2A-EN-NEXT:    s_addk_i32 s32, 0x400
 ; GFX90A-V2A-EN-NEXT:    v_writelane_b32 v40, s31, 1
-; GFX90A-V2A-EN-NEXT:    .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
+; GFX90A-V2A-EN-NEXT:    .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
 ; GFX90A-V2A-EN-NEXT:    s_getpc_b64 s[16:17]
 ; GFX90A-V2A-EN-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
 ; GFX90A-V2A-EN-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
@@ -3240,7 +3240,7 @@ define hidden void @func_call_clobber() #0 {
 ; WAVE32-NEXT:    v_writelane_b32 v40, s30, 0
 ; WAVE32-NEXT:    s_addk_i32 s32, 0x200
 ; WAVE32-NEXT:    v_writelane_b32 v40, s31, 1
-; WAVE32-NEXT:    .cfi_llvm_vector_registers 16, 1791, 0, 32, 1791, 1, 32
+; WAVE32-NEXT:    .cfi_llvm_vector_registers 16, 1576, 0, 32, 1576, 1, 32
 ; WAVE32-NEXT:    s_getpc_b64 s[16:17]
 ; WAVE32-NEXT:    s_add_u32 s16, s16, ex@rel32@lo+4
 ; WAVE32-NEXT:    s_addc_u32 s17, s17, ex@rel32@hi+12
diff --git a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
index bc928041ed750..51300c363e611 100644
--- a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
@@ -493,36 +493,36 @@ define weak_odr void @test(i32 %0) !dbg !34 {
 ; CHECK-NEXT:    buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
 ; CHECK-NEXT:    .cfi_llvm_vector_offset 2600, 32, 17, 64, 0
 ; CHECK-NEXT:    v_writelane_b32 v41, s34, 0
-; CHECK-NEXT:    .cfi_llvm_vector_registers 66, 2622, 0, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 66, 2601, 0, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s35, 1
-; CHECK-NEXT:    .cfi_llvm_vector_registers 67, 2622, 1, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 67, 2601, 1, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s36, 2
-; CHECK-NEXT:    .cfi_llvm_vector_registers 68, 2622, 2, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 68, 2601, 2, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s37, 3
-; CHECK-NEXT:    .cfi_llvm_vector_registers 69, 2622, 3, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 69, 2601, 3, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s38, 4
-; CHECK-NEXT:    .cfi_llvm_vector_registers 70, 2622, 4, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 70, 2601, 4, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s39, 5
-; CHECK-NEXT:    .cfi_llvm_vector_registers 71, 2622, 5, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 71, 2601, 5, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s48, 6
-; CHECK-NEXT:    .cfi_llvm_vector_registers 80, 2622, 6, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 80, 2601, 6, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s49, 7
-; CHECK-NEXT:    .cfi_llvm_vector_registers 81, 2622, 7, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 81, 2601, 7, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s50, 8
-; CHECK-NEXT:    .cfi_llvm_vector_registers 82, 2622, 8, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 82, 2601, 8, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s51, 9
-; CHECK-NEXT:    .cfi_llvm_vector_registers 83, 2622, 9, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 83, 2601, 9, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s52, 10
-; CHECK-NEXT:    .cfi_llvm_vector_registers 84, 2622, 10, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 84, 2601, 10, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s53, 11
-; CHECK-NEXT:    .cfi_llvm_vector_registers 85, 2622, 11, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 85, 2601, 11, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s54, 12
-; CHECK-NEXT:    .cfi_llvm_vector_registers 86, 2622, 12, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 86, 2601, 12, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s55, 13
-; CHECK-NEXT:    .cfi_llvm_vector_registers 87, 2622, 13, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 87, 2601, 13, 32
 ; CHECK-NEXT:    v_writelane_b32 v41, s30, 14
 ; CHECK-NEXT:    v_writelane_b32 v41, s31, 15
-; CHECK-NEXT:    .cfi_llvm_vector_registers 16, 2622, 14, 32, 2622, 15, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 16, 2601, 14, 32, 2601, 15, 32
 ; CHECK-NEXT:    s_mov_b64 s[48:49], s[4:5]
 ; CHECK-NEXT:    ;DEBUG_VALUE: dummy:dummy <- undef
 ; CHECK-NEXT:  .Ltmp0:
diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
index e6d93d857d5a0..c7f751dd30e33 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
@@ -230,7 +230,7 @@ define fastcc i32 @foo() {
   ; CHECK-NEXT:   $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
   ; CHECK-NEXT:   $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc
   ; CHECK-NEXT:   $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31
-  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr127, 0, 32, $vgpr127, 1, 32
+  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr40, 0, 32, $vgpr40, 1, 32
   ; CHECK-NEXT:   BUNDLE implicit-def $sgpr16_sgpr17, implicit-def $sgpr16, implicit-def $scc, implicit-def $sgpr17 {
   ; CHECK-NEXT:     $sgpr16_sgpr17 = S_GETPC_B64
   ; CHECK-NEXT:     $sgpr16 = S_ADD_U32 internal $sgpr16, target-flags(amdgpu-gotprel32-lo) @bar + 4, implicit-def $scc
diff --git a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
index da30190663457..a87f8289e9d4b 100644
--- a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
@@ -233,7 +233,7 @@ define hidden void @_ZL3barv() #0 !dbg !1644 {
 ; CHECK-NEXT:    s_add_i32 s32, s32, 0x400
 ; CHECK-NEXT:    v_writelane_b32 v40, s30, 0
 ; CHECK-NEXT:    v_writelane_b32 v40, s31, 1
-; CHECK-NEXT:    .cfi_llvm_vector_registers 16, 2623, 0, 32, 2623, 1, 32
+; CHECK-NEXT:    .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32
 ; CHECK-NEXT:  .Ltmp0:
 ; CHECK-NEXT:    .loc 0 31 3 prologue_end ; lane-info.cpp:31:3
 ; CHECK-NEXT:    s_getpc_b64 s[16:17]
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
index b71a9eeef208e..2107c7bd527fc 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
@@ -91,140 +91,140 @@ body:             |
   ; GCN-NEXT:   frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02
   ; GCN-NEXT:   $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24, implicit-def dead $scc
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr4, $vgpr255, 0, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr4, $vgpr2, 0, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr5, $vgpr255, 1, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr5, $vgpr2, 1, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr6, 2, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr6, $vgpr255, 2, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr6, $vgpr2, 2, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr7, 3, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr7, $vgpr255, 3, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr7, $vgpr2, 3, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr8, 4, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr8, $vgpr255, 4, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr8, $vgpr2, 4, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr9, 5, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr9, $vgpr255, 5, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr9, $vgpr2, 5, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr10, 6, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr10, $vgpr255, 6, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr10, $vgpr2, 6, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr11, 7, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr11, $vgpr255, 7, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr11, $vgpr2, 7, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr12, 8, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr12, $vgpr255, 8, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr12, $vgpr2, 8, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr13, 9, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr13, $vgpr255, 9, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr13, $vgpr2, 9, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr14, 10, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr14, $vgpr255, 10, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr14, $vgpr2, 10, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr15, 11, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr15, $vgpr255, 11, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr15, $vgpr2, 11, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr16, 12, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr16, $vgpr255, 12, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr16, $vgpr2, 12, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr17, 13, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr17, $vgpr255, 13, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr17, $vgpr2, 13, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr18, 14, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr18, $vgpr255, 14, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr18, $vgpr2, 14, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr19, 15, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr19, $vgpr255, 15, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr19, $vgpr2, 15, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr20, 16, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr20, $vgpr255, 16, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr20, $vgpr2, 16, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr21, 17, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr21, $vgpr255, 17, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr21, $vgpr2, 17, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr22, 18, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr22, $vgpr255, 18, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr22, $vgpr2, 18, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr23, 19, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr23, $vgpr255, 19, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr23, $vgpr2, 19, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr24, 20, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr24, $vgpr255, 20, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr24, $vgpr2, 20, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr25, 21, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr25, $vgpr255, 21, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr25, $vgpr2, 21, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr26, 22, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr26, $vgpr255, 22, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr26, $vgpr2, 22, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr27, 23, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr27, $vgpr255, 23, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr27, $vgpr2, 23, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr28, 24, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr28, $vgpr255, 24, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr28, $vgpr2, 24, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr29, 25, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr29, $vgpr255, 25, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr29, $vgpr2, 25, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr64, 26, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr255, 26, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr2, 26, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr65, 27, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr255, 27, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr2, 27, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr66, 28, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr255, 28, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr2, 28, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr67, 29, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr255, 29, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr2, 29, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr68, 30, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr255, 30, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr2, 30, 32
   ; GCN-NEXT:   $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr69, 31, $vgpr2
-  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr69, $vgpr255, 31, 32
+  ; GCN-NEXT:   frame-setup CFI_INSTRUCTION llv...
[truncated]

[AMDGPU][MC] Replace shifted registers in CFI instructions

0982e15

slinder1 mentioned this pull request Oct 22, 2025

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs #164725

Open

slinder1 assigned kzhuravl, epilk, SLTozer, adrian-prantl, OCHyams and jmorse Oct 22, 2025

slinder1 marked this pull request as ready for review October 22, 2025 22:39

llvmbot added backend:AMDGPU llvm:codegen debuginfo llvm:mc Machine (object) code labels Oct 22, 2025

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[AMDGPU][MC] Replace shifted registers in CFI instructions #164726

[AMDGPU][MC] Replace shifted registers in CFI instructions #164726

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slinder1 commented Oct 22, 2025

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[AMDGPU][MC] Replace shifted registers in CFI instructions #164726

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slinder1 commented Oct 22, 2025 •

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